Nowadays, integrated circuits (ICs) are capable of performing multiple functions, as facilitated by the ability to integrate millions of semiconductor devices such as transistors, resistors and the like onto a substrate. In fact, the complexity of such ICs has become such that distributed design approaches have been developed in which functional blocks have been defined as building blocks of the IC, with the IC being designed by the selection of predefined functional blocks. An example of such a design strategy is the System-on-Chip (SoC) approach, where multiple functional blocks, also referred to as cores, are grouped together during the design process to build an IC having the desired functionality. This approach reduces the complexity of the design task, thus reducing the time-to-market of such ICs.
A problem associated with complex ICs such as SoCs is that due to the high number of power-consuming semiconductor devices in the circuit, the overall power consumption of the IC may be unacceptably high, for instance because the power source of the IC is a battery in which case power consumption should be limited to extend the battery life or because its peak power consumption can in fact damage the IC by overheating.
Consequently, efforts have been made to come up with innovative solutions to reduce the power consumption of such complex ICs. Such innovative solutions include power gating, in which a functional block is powered down to a sleep mode or completely disconnected from the power supply when not being used, and multiple supply voltage solutions, where different circuit parts such as individual cores are powered from separate power supplies, and combinations of these solutions.
The application of multiple supply voltages allows each circuit part to operate at its own optimal supply voltage that matches its desired performance, thus optimizing overall system performance and power consumption. The power gating functionality may be used to reduce the overall IC power consumption by minimizing the leakage currents from an idle circuit part. In the remainder of this application, the combination of the multiple supply voltage approach and the power gating concept will be referred to as multiple power domains.
Multiple power domain ICs typically comprise interfacing circuitry in between power domains, or in between the power domain and the chip boundary. This interface circuitry concerns voltage level converters, also known as level shifters, and clamp circuits. A level shifter translates one voltage level to another voltage level, for example, from a low (0.9V) to a high-supply (1.2V) voltage or vice versa.
Clamp circuits are used to provide a defined logic level while a circuit part is in standby operation, e.g. in a power gated mode. In this case, the internal nodal voltages of the circuit part are floating. The purpose of both level shifters and clamp circuits is to prevent short-circuit current in the receiving circuit part, since such short-circuit currents may give significantly contribute to the overall leakage current of the IC.
In modern system-on-chip (SoC) designs, the functional blocks, i.e. cores, are deeply embedded in the IC such that the core terminals are not directly accessible from the SoC pins. This necessitates the existence of test-access paths from the SoC primary pins to an embedded core and vice versa with sufficient bandwidth to fulfil the test requirement of the core.
In case of core-based testing or power domain based testing, every power domain (or core) is isolated from its environment by means of an isolation shell or wrapper. Every functional connection going in and out of the wrapper has a wrapper isolation cell, which will also be simply referred to as a wrapper cell in this application. An example of such a wrapper is the CTAG TestShell or IEEE 1500 wrapper, which is a wrapper that is compliant with the IEEE 1500 standard for testing digital SoC ICs.
The wrapper cells provide controllability and observability at the core terminals. In principle there is one wrapper cell for every core terminal, although some core terminals do not have a wrapper cell associated with them. There are multiple types of wrapper cells, e.g., depending on the direction of core terminals, such as input, output, and bi-directional. The wrapper cells can be implemented from basic logic gates from the digital standard library.
In single supply voltage environments, the test hardware including the wrappers is powered by the same power supply as the core. However, for an IC comprising multiple power domains, this powering strategy must be reconsidered, because the core supply may be power-gated while at least a part of the wrapper, for instance its bypass register, needs to be active because it forms part of the communication path to or from another core under test.
In addition, the wrappers must be able to cope with the different signal voltages that are the consequence of the multiple power domains. This implies the need for level shifters in the functional connections between wrappers. A possible implementation of such level shifters has been proposed by Synopsys. In this proposed implementation, level shifters have been placed between wrapped cores. This allows a system integrator to decide which of the functional connections need level shifting functionality. An alternative is to have a level shifter as part of the unwrapped core. However, both these approaches have the considerable disadvantage that knowledge of the overall design is required to be able to correctly place the level shifters. In addition, the designer may need to add clamping circuitry to avoid floating signal values rippling to other cores when power gating is activated. This again requires knowledge of the system, which further complicates the design process.